Field of Invention
The present invention relates generally to the field of high current density access devices. More specifically, the present invention is related to back end of line (BEOL) compatible high current density access devices for high density arrays of electronic components.
Discussion of Related Art
In order to increase the density of memory technologies (both volatile and nonvolatile), a crosspoint design is preferred. In such an optimized design, the wordline and bitlines (henceforth referred to as memory lines) run at minimum pitch=2F, where F refers to the lithographic minimum feature size (for example, 32 nm), and a storage element is placed between these perpendicularly oriented memory lines at their crosspoints. Two possible designs exist in such memory technologies:
(a) A Nano-Crossbar Design: Refers to a design where the memory lines run at sublithographic pitches. In this design, memory cell area is reduced from 4F2 to 4Fs2 where 2Fs is the nanoscale pitch and Fs<<F, where F is the above-mentioned lithographic minimum feature size. Previous studies detail how these sublithographic features are interfaced to lithographically defined wordline and bitline driver/decoder circuits.
(b) A 3D Design: Refers to a design where the memory lines run at lithographic pitches, with multiple layers of memories being provided. The effective area of these cells is therefore 4F2/n, where n is the number of 3D layers.
In either design case described above, two device components are needed at the intersection of the memory lines:
(a) A Memory Element: Refers to an element that is used to store data/information. Many options exist here (including, for example, phase change memory (PCM), MRAM, solid electrolyte memory, FeRAM, etc.), with one promising memory node material being PCM.
(b) A Rectifying Element or Access Device: Since a transistor is not provided at every crosspoint, a device is needed to rectify (exhibit nonlinearity). This ensures that the memory cells that lie on unselected wordlines and bitlines are not inadvertently programmed or shorted to each other and do not leak any significant amount of current.
For most promising memory materials, programming current densities that are of the order of 107-108 A/cm2 are needed for critical dimensions (CDs) down in the range of 20-40 nm. FIG. 1 illustrates a graph of reset current and reset current density versus critical dimension for resistive memory elements that controllably change phase upon the passage of current. It can be seen from FIG. 1 that currents reduce with scaling but current densities increase substantially due to thermal losses that increase with scaling.
It should be noted that since the PCM CD is smaller than F (to minimize reset currents and to minimize proximity effects), the effective current density in the series diode is somewhat smaller. If the PCM CD ranges from 0.5F (¼th of the pitch) to 0.66F (⅓rd of the pitch), the reset currents in the diode would be 2.25× to 4× smaller. However, such current densities are still extremely high.
The best known single-crystal silicon p-n and Schottky diodes that can be used for rectification provide 1-2×107 A/cm2 at low voltages. This limit comes from a number of different factors including high level injection effects in p-n junctions, series resistance of doped region(s), etc. This is an order of magnitude smaller than what is needed for most resistive memory elements. In addition, the quality of the diodes that can be fabricated in middle-of-line (MOL) or back end of line (BEOL) lower temperature processes are typically much worse since they have to be made in amorphous or polycrystalline silicon that has much lower mobility. These considerations prevent the use of p-n junctions in either single-crystal silicon or other silicon materials as rectifiers for high-current memory elements (especially in 3D).
In addition, the current through unselected cells has to be small to prevent array-disturbs and reduce programming power. Typically a rectification ratio well in excess of 10 times the number of elements on the WL or BL is needed. In other words, for typical Mbit arrays, a rectification ratio of 10000 or above is needed (preferably exceeding 107). The rectification ratio is typically a function of the bias since the leakage is typically a function of bias.
Solutions developed by the current assignee involves the use of a solid electrolyte (SE) device element (see, for example, U.S. Pat. No. 7,382,647) as an access (diode) element for PCM. The advantage of such approaches involve the ON/OFF ratio, as the SE can provide very high currents in the ON state (since it has a metallic filament that bridges the two electrodes) and very low OFF currents. However, disadvantages with this approach include:
(a) the need for an explicit erase step to erase the filament, wherein such an erase step can be quite slow (for example, 100's of microseconds are needed to erase a thick filament), and
(b) the low reliability/endurance of the SE element during high current programming.
There is therefore the need for an access device (for use as an access element for semiconductor memory arrays) that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing (i.e., at sub 400° C.).
In addition, there are other electronic applications involving dense arrays of components, such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs) arrays, which require an access element that would provide single (or multiple) element addressability while blocking multiple current paths through half-selected or unselected elements.
In typical Active-Matrix LCD (AMLCD) displays, each pixel has a Thin Film Transistor (TFT) in series with a pixel electrode and a storage capacitor. The TFT, which functions as the access element, can be fabricated using amorphous silicon (a-Si), high-temperature polysilicon (HTPS) or Low Temperature Polysilicon (LTPS). The disadvantage of the a-Si approach is that the mobility of carriers is very low in such devices. The high-temperature polysilicon approach is compatible only with quartz substrates (which are much more expensive and limited to 8-10 inch diagonal sizes) as opposed to ordinary glass (limited to 600° C.). The LTPS approach uses a laser annealing process and has mobilities 200× higher than the amorphous silicon versions but is still lower than the HTPS approach. In addition, the a-Si approach does not allow the integration of drive electronics (that drive the row and the column busses) onto the glass itself requiring the use of a separately fabricated LCD driver circuit that is attached to the glass via TAB (Tape Automated Bonding). In order to achieve higher density displays (i.e., to reduce pixel size), it is desired to increase the drive current of these access elements. This also allows the integration of the driver circuitry onto the glass itself further reducing integration costs. A thin film diode (TFD) access element is preferred because it further reduces pixel size but has found limited use due to device uniformity and threshold stability issues.
Therefore, what is needed is a new thin film diode (TFD) or access device material with high current densities and with limited variability for use in TFD-based AMLCD displays. Further, there is also a need for a thin film diode (TFD) for Active-Matrix OLED Displays.
Embodiments of the present invention are an improvement over prior art systems and methods.